FIGS. 1 to 3 are views illustrating manufacturing processes of a symmetric semiconductor device.
Referring to FIG. 1, a device isolation region 11 is formed in a semiconductor substrate 10 through a Shallow Trench Isolation (STI) technique, and then an insulation layer 12 and a polysilicon layer 13 are stacked thereon. Based on the device isolation region 11, one side of the semiconductor substrate 10 is a region where an N-type Metal Oxide Semiconductor (NMOS) device is to be formed, and the other side of the semiconductor substrate 10 is a region where a P-type MOS (PMOS) device is to be formed.
As shown in FIG. 2, gate insulation layers 12a and 12b and gate electrodes 13a and 13b are formed in the NMOS region and the PMOS region, respectively, by patterning the insulation layer 12 and the polysilicon layer 13. Then, symmetric Lightly Doped Drain (LDD) regions 14a and 14b are formed through an ion implantation process.
Next, as shown in FIG. 3, spacers 16a and 16b are formed on the sidewalls of the gate electrodes 13a and 13b, and source and drain regions 15a and 15b are formed in each of the NMOS region and PMOS region through an ion implantation process. However, the following limitations may occur due to the structure of the symmetric semiconductor device.
First, the symmetric LDD structure, where source and drain terminals adjacent to opposed sides of the gates have the same size, may cause characteristic sub-threshold deterioration, and due to this, the drive current becomes lower in a saturation state.
Second, in an inversion mode (where sub-threshold current[s] occur), an LDD region of the source terminal may adversely affect the swing characteristic[s] of the device, and the parasitic capacitance of an overlapping portion of the gate and the LDD region may slow down an operational speed of the device. For example, in a flip-flop circuit that includes symmetric semiconductor devices, due the influence of the drive current and the capacitance(s), an edge portion of a swing characteristic graph may not have a vertical structure, but rather, may have a parabolic structure. Additionally, the propagation delay time may increase. Since the propagation delay time is proportional to the capacitance and is inversely proportional to the drive current of each MOS region, there may be a limitation in reducing the propagation delay time in a circuit including the symmetric semiconductor device(s).
Third, the junction depth of the active region is a very important factor for controlling the line width of the device and the effective channel length of a gate electrode. Therefore, the junction depth may be adjusted using In/Sb (e.g., heavy) ion implantation and Laser Spike Anneal (LSA) processes.
However, even if the junction depth is adjusted through the above techniques, the Short Channel Effect (SCE) and Reverse Short Channel Effects (RSCE) such as Gate Induced Drain Leakage (GIDL) and Drain Induced Barrier Lowering (DIBL) may occur.
Additionally, since the drive voltage is relatively high in comparison to the size of a highly-integrated semiconductor device, an injected electron may intensely accelerate in or near a source region due to the potential gradient state of the drain. Also, Hot Carrier Instability (HCI) phenomena may occur. Therefore, it becomes very difficult to control the threshold voltage of a symmetric semiconductor device.